The present invention relates to a phase detector and utilization of the phase detector for synchronization of a digital data signal with a clock signal, e.g. in clock and data recovery circuits.
Upon transmission of digital data at a high data rate, e.g. via an optical transmission line, it is typically required to synchronise the transmitted data bits with a clock signal. Typically the clock signal is generated from the received data signal in a clock and data recovery circuit. Noise tolerance is an essential feature of clock and data recovery circuits.
The ITU-T has specified jitter parameters that are determined in the frequency domain. Jitter tolerance of receiving equipment is defined as the sinusoidal peak-to-peak phase modulation which causes a 1 dB optical penalty.
For example, when characterising a clock and data recovery component, white noise is added to the input signal. By varying the signal-to-noise ratio, an input sensitivity curve of the clock and data recovery component is obtained. Then, the signal-to-noise ratio is set to e.g. a bit error rate of 10xe2x88x929, the input signal level is increased by 2 dB (electrical), and the peak-to-peak jitter amplitude that recovers the 10xe2x88x929 bit error rate is determined. In known clock and data recovery circuits, the determined values will depend on the processed data pattern and its transition density.
The jitter transfer function is defined as the ratio of jitter at the output relative to jitter applied to the input versus frequency.
The timing characteristics of a received data signal and a clock signal depend on circuit component characteristics, circuit temperature, etc. Therefore, in the field of high speed data communication, it is not a straight forward task to design an electronic circuit providing appropriate synchronisation between the received data signal and a corresponding clock signal so that the above-mentioned sampling of the data signal takes place at the centre of the bit period.
Adjustable circuits are known requiring adjustment of each individual circuit during manufacturing to obtain proper synchronisation of data bits and a clock signal. Such a procedure requires a priori knowledge of the bit frequency and leads to an expensive and complex product.
More recently, electronic circuits have been developed that automatically synchronise a digital data signal with a clock signal. In the known circuits a phase detector compares the phases of the data signal and the clock signal and generates an error output signal that is proportional to the phase difference between the two signals. The error output signal is connected to a controlled oscillator that generates a clock signal and adjusts the actual frequency of the clock signal in response to the error output signal. Thereby, the data signal is synchronised to the clock signal, i.e. the data signal is phase locked to the clock signal, so that the data signal is sampled approximately at the centre of each bit by the clock signal.
It is an object of the present invention to provide a bang bang phase detector for use in a circuit for synchronising a digital data signal with a clock signal, such as clock and data recovery circuits, etc, and having improved characteristics including jitter tolerance and jitter transfer over known bang bang phase detectors.
It is a further object of the present invention to provide a bang bang phase detector with characteristics that are substantially invariant to the transition density of the phase detector input signals.
It is another object of the present invention to provide a bang bang phase detector that generates an output signal that, when used as a control signal in a phase or frequency locked loop, keeps the gain of the control loop substantially invariant to the transition density of the phase detector input signals.
According to a first aspect of the invention the above and other objects are fulfilled by provision of a phase detector for detection of a phase difference between a first signal and a second signal that comprises a first logic circuit for detection of a data transition of the first signal, and a second logic circuit that generates a logic output signal of a first logic value upon detection of a data transition of the first signal if a transition of the second signal occurs before the transition of the first signal and of a second logic value if the transition of the second signal occurs after the transition of the first signal.
Preferably, the phase detector further comprises a third logic circuit that, in the absence of a data transition of the first signal, maintains the logic output signal at a constant value equal to the value generated at the previous data transition of the first signal.
The logic output signal may be a strobed logic output signal. The strobe signal may be generated from the second signal.
Preferably, the second signal is a clock signal used for sampling of the first signal.
The phase detector may for example be used in a circuit for synchronization of a digital data signal (Din) comprising a controlled oscillator for generation of a clock signal (Ck), and a sampling circuit for sampling the data signal by means of a clock signal (Ck), a phase locked loop including the controlled oscillator for phase locking the internal clock signal (Ck) to the data signal (Din) so that the latter is samples approximately at the center of every bit. The controlled oscillator adjusts the frequency of the clock signal (Ck) in response to the output values of the phase detector.
According to a second aspect of the invention, a phase detection method is provided for detection of a phase difference between a first signal and a second signal, comprising the steps of detection of absence or presence of a data transition of the first signal, and upon detection of a data transition of a first signal, generation of a logic output signal of a first logic value if a transition of the second signal occurs before the transition of the first signal or generation of a second logic value if the transition of the second signal occurs after the transition of the first signal, and, in the absence of a data transition of the first signal, maintaining the logic output signal at the value generated at the previous data transition of the first signal.
The method may further comprise the step of strobing the logic output signal. The strobe signal may be generated from the second signal.
The method may also comprise the step of sampling the first signal with the second signal.